A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series–Parallel Conversion With Less Number of Components

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—The aim of this paper is to present a new 6 structure for switched-capacitor multilevel inverters 7 (SCMLIs) which can generate a great number of voltage 8 levels with optimum number of components for both sym-9 metric and asymmetric values of

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      I    E    E    E     P   r   o   o    f IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1 A New Cascaded Switched-Capacitor MultilevelInverter Based on Improved Series–ParallelConversion With Less Number of Components 123 Elyas Zamiri, Naser Vosoughi, Seyed Hossein Hosseini,  Member, IEEE  , Reza Barzegarkhoo,and Mehran Sabahi 45 Abstract  —The aim of this paper is to present a new 6 structure for switched-capacitor multilevel inverters 7 (SCMLIs) which can generate a great number of voltage 8 levels with optimum number of components for both sym- 9 metric and asymmetric values of dc-voltage sources. The 10 proposed topology consists of a new switched-capacitor 11 dc/dcconverter(SCC)thathasboostabilityandcancharge 12 capacitors as self-balancing by using the proposed binary 13 asymmetrical algorithm and series–parallel conversion 14 of power supply. The proposed SCC unit is used in new 15 configuration as a submultilevel inverter (SMLI) and then, 16 these proposed SMLIs are cascaded together and create a 17 new cascaded multilevel inverter (MLI) topology that is able 18 to increase the number of output voltage levels remarkably 19 without using any full H-bridge cell and also can pass 20 the reverse current for inductive loads. In this case, two 21 half-bridge modules besides two additional switches are 22 employed in each of SMLI units instead of using a full 23 H-bridge cell that contribute to reduce the number of 24 involved components in the current path, value of blocked 25 voltage, the variety of isolated dc-voltage sources, and as 26 a result, the overall cost by less number of switches in 27 comparison with other presented topologies. The validity 28 of the proposed SCMLI has been carried out by several 29 simulation and experimental results. 30 Index Terms  —Cascade sub-multilevel inverter (CSMLI), 31 self-chargebalancing,series–parallelconversion,switched 32 capacitor. 33 I. I NTRODUCTION 34 M ULTILEVEL inverters (MLIs) are known as one of the 35 most popular solutions to improve the performance of  36 renewable energy systems, electric vehicles (EVs), and other 37 innovative power electronic utilities in medium and high power 38 applications [1], [2]. These converters can generate a stair- 39 case voltage waveform at the output with high quality and 40 desired spectrum. The desired output voltage is synthesized by 41 Manuscript received February 14, 2015; revised October 3, 2015;accepted December 1, 2015.E. Zamiri, N. Vosoughi, S. H. Hosseini, and M. Sabahi are with theFaculty of Electrical and Computer Engineering, University of Tabriz,Tabriz 51666-16471, Iran (e-mail: elyaszamiry@yahoo.com; naser.vosoughi@yahoo.com; hosseini116j@yahoo.com; sabahi@tabrizu.ac.ir).R. Barzegarkhoo is with the Faculty of Electrical Engineering, SahandUniversity of Technology (SUT), Tabriz 53317-11111, Iran (e-mail:barzegar_sina@yahoo.com.au).Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TIE.2016.2529563 appropriate switching of several dc-voltage links, which leads  42 to decrease voltage stresses on switches and total harmonic  43 distortion (THD) [3], [4].  44 In general, there are three conventional types of MLI config-  45 urations categorized into diode clamped (DCMLI) [5], flying  46 capacitors (FCMLI) [6], [7], and cascade H-bridge (CHB)  47 topologies, which can be divided into two entire divisions based  48 on symmetric and asymmetric values of dc power supplies  49 [8]–[10].  50 Although these converters have a lot of advantages over the  51 classic inverters, using aforementioned conventional topologies  52 need more number of required power switches, power sup-  53 plies, and large capacitor banks. Furthermore, voltage of the  54 capacitors tends to be discharged theoretically and therefore  55 charge balancing control processing is necessary. There have  56 been several suggested charge balancing circuits to control the  57 capacitors’ voltage [11]–[17].  58 References [11]–[13] could regulate the duty cycle of dc  59 bus capacitors for FCMLIs by using the existing redundancy  60 switching states (RSSs). In this case, the accuracy of the pro-  61 posed approach depends on designing a closed-loop control  62 system. Also, [14] presented a phase-shift modulation approach  63 to obviate the discharging problem in a capacitor-based seven-  64 level CHB topology supplied by one dc-voltage source for main  65 unit and one floating capacitor for auxiliary unit. Here, the main  66 and auxiliary power switches have to drive by fundamental  67 and high switching frequencies, respectively. Meanwhile, [15]  68 presented a triplen harmonic compensatory method based on  69 fundamental switching strategy to extend the range of modula-  70 tion index for three-phase utility of seven-level CHB topology.  71 Using the resonant switched-capacitor circuit (RSCC) as an  72 external voltage balancing network can also prevent this prob-  73 lem for DCMLIs [16].  74 Nowadays, many researchers have presented numerous  75 developed structures of MLIs with less number of key com-  76 ponents, such as number of required switches, gate drivers,  77 power supplies, and so on [18]–[20]. One of the most partic-  78 ular schemes of them is switched-capacitor multilevel inverters  79 (SCMLIs). These converters can produce more output voltage  80 levels with less number of required power supplies [21]–[24].  81 SCMLIs contain several capacitors and switches, which can  82 connect dc power supply to ac output and are able to decrease  83 the burden of power supply to achieve higher number of voltage  84 levels.  85 0278-0046 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.      I    E    E    E     P   r   o   o    f 2 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Nevertheless, to attain the greater number of output voltage 86 levels with less number of power semiconductors and simple 87 commutation, a new type of SCMLIs have been emerged using 88 the series–parallel switching strategy (SCISPC) [25], [26]. The 89 distinctive features of these types of inverters are that they can 90 increase the flexibility of systems by switching between several 91 capacitors in series or parallel modes and therefore can trans- 92 fer more input power to the output. In this way, [27] and [28] 93 presented a new family of cascade and hybrid SCISPC topolo- 94 gies that have a modular structure and generate more output 95 voltage levels with least of switches. But, such structures have 96 used the full H-bridge units with isolated dc-voltage sources to 97 change the polarity of output voltage waveform, which makes 98 more conducting loss through the current path components and 99 increases the number of power switches. 100 In this paper, initially, a new switched-capacitor dc/dc con- 101 verter (SCC) is presented which can switch as conventional 102 series/parallel conversion and generate multiple dc-link volt- 103 ages with optimum components. In this case, voltage of all 104 capacitors is filled by binary asymmetrical pattern without 105 using any auxiliary circuits. At the next, a new submultilevel 106 inverter (SMLI) topology presents, which is performed based 107 on the proposed SCC unit and without using full H-bridge cell. 108 In addition, this structure is suitable for an inductive load with 109 the capability to pass the reverse current. After that, the pro- 110 posed submultilevel modules are cascaded with each other and 111 createmoreoutputvoltagelevels.Therefore,mostoftheparam- 112 eters such as number of required switches, diodes, maximum 113 current path components, and value of total blocked or stand- 114 ing voltage are improved. In order to prove the performance 115 of the proposed circuit, variety number of comparisons with 116 other recently suggested topologies has been done in fair con- 117 ditions and also analysis of theoretical power losses is given. 118 Finally, validity of the proposed topology is shown by several 119 experimental and simulation results. 120 II. P ROPOSED  SCC 121 Fig. 1(a) shows the basic circuit of the proposed SCC. This 122 circuit is named by basic unit and contains one dc power supply, 123 one capacitor, one passive power diode, and two active power 124 switches. Photovoltaic (PV) cells, batteries, and fuel cells can 125 be used as a power supply in this structure. Fig. 1(b) and (c) 126 shows that how to carry out the charging and discharging oper- 127 ations for capacitor  C  . Switches  S  a  and  S  b  are used in series 128 and parallel conversions, respectively. As it can be inspected, 129 when the switch  S  b  becomes  ON , the capacitor  C   is charged 130 to  V   dc  and when the switch  S  a  turns  ON , the diode becomes 131 reverse biased and capacitor is discharged. In this mode, the 132 power supply energy and stored energy of   C   are transferred 133 to the output. It is obvious that, basic unit does not need any 134 extra charge balancing control circuits and complicated com- 135 mutation methods, which is counted as a great merit of this 136 structure [28]. Also, it is remarkable that, the internal resistance 137 of power diode and capacitor can damp the unequal voltage 138 between capacitor and dc-voltage source during the charging 139 operation, which leads to introduce an effective and practical 140 power circuit. 141 Fig. 1. (a) Basic series/parallel unit. (b) Capacitor discharging mode.(c) Capacitor charging mode. F1:1F1:2 Fig. 2. Proposed SCC.  F2:1 In the next step, proposed dc/dc converter is made by  142 extended connection of this basic unit. Then, a staircase volt-  143 age waveform is generated at the output with the capability of   144 passing the reverse current for inductive load and can be used  145 as a part of inverters. Fig. 2 shows the circuit configuration of   146 the proposed converter. In order to charge all the capacitors  147 and generate output voltage waveform, the switches  S  ai ( i  =  148 1 , 2 ,...,n − 1) ,  S  bi , and  S  ci ( i  = 1 , 2 ,...,n )  are driven by  149 series/parallel conversion or combination of them.  150 In this case, switches  S  ci  are unidirectional power switches  151 without antiparallel diode, which can pass the reverse induc-  152 tive load current and other switches are also unidirectional with  153 internal antiparallel diode. As figure shows, switches  S  ci ( i  =  154 2 , 3 ,...,n )  can be substituted by ordinary power switches and  155 a series diode to counteract the effect of internal antiparallel  156 diode. Table I indicates the different switching and capacitors’  157 states for the proposed SCC.  158 In this table, 0 and 1 mean  OFF  and  ON  switching state  159 and C and D refer to charging and discharging modes for  160 capacitors, respectively. In order to generate more number of   161 output voltage levels with optimum number of components,  162 all the capacitors should be charged by binary asymmetrical  163 algorithm, according to this table in such a way that, in state  164 (1) when switch  S  c, 1  becomes  ON , capacitor  C  1  is charged to  165 V   dc  and this voltage level is transferred to the output through  166 S  a,i ( i  = 1 , 2 ,...,n − 1)  simultaneously.  167 Also in state (2),  C  2  is being charged to  V   dc  + V   c 1  through  168 switch  S  c, 2  and with discharging of   C  1 , second voltage level  169 generates at the output through  S  a,i  and  S  b, 1 , simultaneously,  170      I    E    E    E     P   r   o   o    f ZAMIRI  et al. : NEW CASCADED SCMLI 3 TABLE I T1:1 S WITCHING AND  C APACITORS  S TATES OF THE  P ROPOSED  SCC T1:2 which is equal to  2 V   dc . After this moment, without entering 171 other capacitors into the circuit, voltage level of   3 V   dc  can be 172 transferred to the output by stored voltage of   C  2  and constant 173 dc-voltage source. In this moment,  C  1  is again charged by dc- 174 voltage source directly and for the next voltage level, this stored 175 voltagebesidestheacrossvoltageof  C  2  andconstantdc-voltage 176 source are transferred to the output, which is equalized to  4 V   dc 177 and this consecutive operation continues so on. 178 The prominent feature of the proposed circuit isthat by enter- 179 ing the next capacitors into the circuit and also continuing the 180 series–parallel switching strategy, the number of output voltage 181 levels is enhanced as binary manner from  V   dc  to  2 n V   dc . 182 It is important to note that, always at each of voltage steps, 183 the pertinent capacitor of previous steps must be connected as 184 parallel to keep on the charging operation. Therefore, if we 185 assume the number of capacitors equal to  n , the stored voltage 186 of each capacitor would be equalized to 187 V   C,k  = 2 k − 1 V   dc ,  for  k  = 1 , 2 ,...,n.  (1)Also from this table, it is obvious that, the proposed SCC 188 is able to generate different positive output voltage levels by 189 self-balancing ability. Now, by considering the proposed over- 190 allstructure(Fig.2),numberofrequiredswitches( N  switch ,u )or 191 gate drivers ( N  Driver ,u ), number of required isolated-gate bipo- 192 lar transistors (IGBTs)  ( N  IGBT ,u ) , power diodes  ( N  diode ,u ) , 193 and output voltage levels  ( N  level ,u )  are calculated by the fol- 194 lowing equations, respectively, 195 N  switch ,u  =  N  Driver ,u  =  N  IGBT ,u  = 3 n − 1  (2) N  diode ,u  =  n  (3) N  level ,u  = 2 n .  (4) Fig. 3. Proposed SMLI configuration.  F3:1 According to (4), the proposed circuit has appropriate perfor-  196 mance as boost capability. This factor can be defined as  197 β   =  V   o, max ,u  V   dc = 2 n .  (5)Moreover, this structure is able to mitigate the total blocked  198 voltage. As is well known, the value of blocked voltage should  199 be tolerated by switches and means standing voltage across of   200 switches, which effects on conduction losses, efficiency, and  201 cost [29]. In this case, the total blocked voltage is formulized by  202 V   block  ,u  = [3(2 n − 1) − 1] V   dc .  (6) III. P ROPOSED  SMLI  203 As it was analyzed before, the proposed SCC generates out-  204 put voltage waveform with positive polarity. Therefore, it is not  205 suitable for inverter applications. In order to change the polarity  206 andcreateanacwaveform,anH-bridgecellcanbeconnectedto  207 the output similar to the other existing structures. However, this  208 cell may increase the number of required IGBTs and the num-  209 ber of involved components in the current path. This paper has  210 not focused on added H-bridge cell and presents a new scheme  211 of SCISP shown in Fig. 3, based on two utilized half-bridges.  212 In order to convert the output polarity of SCC and create  213 all the voltage levels (even and odd) at the output, this struc-  214 ture always requires a pair stage of SCC units. Therefore, the  215 proposed SCISP named as SMLI can produce positive, zero,  216 and negative output voltage levels with six unidirectional power  217 switches and two same units of SCC. As a result,  2 n  capacitors  218 and two isolated dc power supplies are needed for this structure.  219 Now, the number of required IGBTs or gate drivers and the  220 number of power diodes can be expressed as follows:  221 N  IGBTSub =  N  DriverSub = 6 n + 4  (7) N  DiodeSub = 2 n.  (8)Table II indicates  ON  switching states of the proposed SMLI,  222 which is summarized by seven different modes. According to  223 this table, to refrain from short-circuit problems, switches of   224      I    E    E    E     P   r   o   o    f 4 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS TABLE II T2:1 S WITCHING  P ATTERN OF THE  P ROPOSED  SMLI T2:2 ( T  1 ,T  1  ) ,  ( T  2 ,T  2  ) , and  ( T  3 ,T  3  ) , are triggered as comple- 225 mentary operation with each others and should not to be  ON 226 simultaneously. Also, this structure can work on symmetric 227 and asymmetric values of dc-voltage sources. In symmetric 228 structure, all the dc sources are equal and that are different in 229 asymmetric topology. Then, by considering (1), to obtain the 230 maximum number of voltage levels fromasymmetric condition, 231 the value of other isolated dc power supply should conform the 232 following expression: 233 V   dc , 2  = (1 + 2 n ) V   dc , 1 .  (9)Table III indicates the pertinent equations of   N  levelSub , 234 v o, maxSub , and  V   BlockedSub for symmetric and asymmetric forms 235 in the proposed SMLI. In this case, the asymmetric calculations 236 in Table III are done by considering (9). 237 To achieve the greater number of voltage levels, the pro- 238 posed SMLI can be extended by increasing the number of  239 output voltage levels for the proposed SCC. But, this way yields 240 to some identical restrictions due to increase in the voltage 241 drop and existed spikes across each of capacitors especially in 242 high power ratio. To avoid this constraint, the best solution to 243 increase the number of voltage levels is considered by series 244 connection of the proposed SMLIs with each other shown as 245 proposed cascaded submultilevel inverter (CSMLI) in Fig. 4. In 246 this figure, number of cascaded SMLI units is indexed by m . As 247 a result, output voltage of the proposed CSMLI is obtained by 248 v o ( t ) =  v o, 1 ( t ) + v o, 2 ( t ) + ··· + v o,m ( t ) .  (10)It should be noted that, in this case, the number of capacitors 249 thathavebeenusedineachofSCCsisassumedsame.Toreduce 250 the cost, weight, total blocked voltage, and some other identical 251 problems, the required capacitors for each of the proposed SCC 252 units ( n ) is optimized in Section IV. 253 IV. P ROPOSED  I MPROVED  CSMLI 254 In this section, the number of required capacitors in each 255 of the proposed SMLI units is optimized from the view point 256 of maximum produced output voltage levels for the proposed 257 CSMLI with minimum number of IGBTs. This optimization is 258 done based on asymmetric value of dc sources according to (9). 259260 TABLE III  T3:1 D IFFERENT  R ELATED  E QUATIONS FOR THE  P ROPOSED  SMLIT OPOLOGY T3:2T3:3 Fig. 4. Proposed CSMLI.  F4:1 In general, the number of output voltage levels for the  261 proposed CSMLI is obtained by  262 N  level  =  N  levelSub  m (17)where  N  levelSub is the number of output voltage levels for the pro-  263 posed SMLI, which is calculated by (14). Then, (17) can be  264 rewritten as  265 N  level  =  2 n +2 + 2 2 n +1 + 1  m .  (18)Ontheotherhand,therelationof  m intermsof  N  IGBT  (num-  266 ber of required IGBTs for the proposed CSMLI) and  N  IGBTSub is  267 equalized to the following equation:  268 m  =  N  IGBT N  IGBTSub .  (19)Also, by inserting (13) into (18) and (19),  269 N  level  =  2 n +2 + 2 2 n +1 + 1  N  IGBT   6 n +4 .  (20)In order to obtain the optimal number of capacitor from each  270 of SMLIs, the variation of   N  level  against  N  IGBT  for specific  271 number of   n , is curved according to (20) and illustrated by  272 Fig. 5. As this figure shows, for a constant value of   N  IGBT ,  273 N  level  has been maximized when one capacitor is being used.  274 Therefore, with respect to n  = 1 , number of output voltage lev-  275 els, required IGBTs, power diodes, and total value of blocked  276      I    E    E    E     P   r   o   o    f ZAMIRI  et al. : NEW CASCADED SCMLI 5 Fig. 5. Variation of  N  level  against  N  IGBT  for different values of  n . F5:1 Fig. 6. Proposed 17-level structure. F6:1 voltage for the proposed improved CSMLI are obtained for 277 both symmetric and asymmetric conditions and are summa- 278 rized in Table IV. In addition, based on (9), the value of  279 dc-voltage sources in  i th  unit of the proposed CSMLI should 280 be adopted by 281 V   dc 2 ,i  = 3 V   dc 1 ,i  = 3(17 i − 1 ) V   dc , i  = 1 , 2 ,...,m.  (21)Fig. 6 shows an improved CSMLI configuration by consid- 282 ering  m  = 1 , which leads to generate 17-level output voltage 283 based on the proposed asymmetric topology. In this circuit, the 284 values of dc isolated power supplies are set on  V   dc  and  3 V   dc 285 according to (9). Table V shows the switching pattern of the 286 proposed 17-level inverter. 287 In this case, all the switches are driven by fundamental 288 switching frequency, whereas the sinusoidal reference voltage 289 is compared with some available dc-voltage levels and create 290 the related gate switching pulses. The most advantage of this 291 switching method is referred to low switching frequency that 292 yields to the reduction of switching loss [29], [30]. Details of  293 fundamental switching modulation strategy are not the objec- 294 tive of this paper. In addition from Table V, it is clear that, to 295 generate each of the output voltage levels, only five switches 296 are being involved in the current path. 297 At this stage, to determine the capacitance of  C  1  and C  2 , two 298 assumptions are considered in which one is related to the output 299 sinusoidal load current with phase difference between output 300 voltage and current  ( ϕ )  and the other is contributed to the same 301 duration in each step of staircase output voltage. Thus, the max- 302 imum discharging amount of each capacitor can be defined as 303 TABLE IV  T4:1 D IFFERENT  R ELATED  C ALCULATIONS OF THE  P ROPOSED  I MPROVED CSMLI T4:2T4:3 TABLE V  T5:1 D IFFERENT  S WITCHING AND  C APACITORS  S TATES OF THE  P ROPOSED 17-L EVEL  I NVERTER T5:2T5:3 (30) in one half-cycles  304 Q Ci  = T    4  − t j   t j I  out  sin(2 πf  S  t − ϕ ) dt, i  = 1 , 2  (30)where  T  ,  f  S  , and  I  out  are the period of one cycle, frequency of   305 output voltage, and amplitude of load current, respectively, and  306 also  t j ,  T  4  − t j  isthetimeintervalcorrespondedtothelongest  307 discharging cycle (LDC) of each capacitors. On the other hand,  308 in the proposed 17-level inverter, this time interval varies for  309 C  1  and  C  2 . According to Table V, the LDC for  C  1  and  C  2  is  310 illustratedbyFig.7.Thus,byconsidering the kV   in  asmaximum  311 allowable voltage ripple, the optimum value of capacitors can  312 be taken by  313 C  opt ,i  ≥ Q Ci kV   in , i  = 1 , 2 .  (31)
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